module midereg(
    input clk,
    input [31:0]ex_pc,
    input [31:0]ex_ins,
    input [3:0] ex_ALUctr,
    input [2:0] ex_Branch,
    input [1:0] ex_Jump,
    input [1:0] ex_RegWr,
    input ex_RegDst,
    input ex_ExtOp,
    input ex_ALUsrc,
    input [1:0] ex_MemWr,
    input ex_MemtoReg,
    input ex_ALUshf,
    input ex_R31wr,
    output reg [31:0] pc,
    output reg [31:0] ins,
    output reg [3:0] ALUctr,
    output reg [2:0] Branch,
    output reg [1:0] Jump,
    output reg [1:0] RegWr,
    output reg RegDst,
    output reg ExtOp,
    output reg ALUsrc,
    output reg [1:0] MemWr,
    output reg MemtoReg,
    output reg ALUshf,
    output reg R31wr
);


always @(posedge clk) begin
   ALUctr = ex_ALUctr;
   Branch = ex_Branch;
   Jump = ex_Jump;
   RegWr = ex_RegWr;
   RegDst = ex_RegDst;
   ExtOp = ex_ExtOp;
   ALUsrc = ex_ALUsrc;
   MemWr = ex_MemWr;
   MemtoReg = ex_MemtoReg;
   ALUshf = ex_ALUshf;
   R31wr = ex_R31wr; 
   pc = ex_pc;
   ins = ex_ins;
end

endmodule // 